Standard Cell Design Methodology & Flow Engineer

Summary

Posted: Mar 4, 2025

Role Number:200576036

Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas and determine how to turn them into reality! You will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking and groundbreaking ideas to the real world. You’ll help design the tools that allow us to bring customers experiences they’ve never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering quality products to market quickly.

Description

Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of talent engineers. In this role on our custom circuits team, you will: – Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements. – Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows – Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification. – Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.

Minimum Qualifications

• BS and a minimum of 10 years of relevant industry experience.

Preferred Qualifications

• At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc.
• Experience with timing modeling of large custom macros and complex sequential flops.
• Exposure to Design For Test, scan concept and write DFT friendly RTL
• Understands all aspects of implementation specification, design, timing, power, and flow automation.
• Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation
• Flow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/Perl
• Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
• Proven understanding of device physics and process.
• Familiar with foundry ecosystem and benchmarking practice.

Pay & Benefits

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $165,500 and $293,800, and your base pay will depend on your skills, qualifications, experience, and location.
  
  Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
  
  Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.