STA Synthesis Engineer

Summary

Posted: Nov 8, 2024

Role Number:200577873

Imagine what you could do here. At Apple, great ideas have a way of becoming great products and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s world class chip is driven by top notch engineers. Are you ready to join our team and help us deliver the next groundbreaking Apple products?

Description

In this highly visible role you will be: – You will excel as you optimize designs to reach ground breaking power, area, timing goals. – Delivery of timing clean, logically equivalent netlists to physical design team. – We will empower you to collaborate with a variety of functional teams to continually question the limitations of technology.

Minimum Qualifications

• Bachelors Degree + 3 Years of Experience

Preferred Qualifications

• STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team.
• Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.
• Embrace technical challenges with your natural passion to innovate.
• Ability to collaborate effectively with different functional teams and strong written/verbal communication.
• Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms.
• Professional experience with ECO implementation, both functional and timing closure.
• Familiarity with simulation, debugging tools, and working closely with DV team.
• Experience with multi-clock and multi-power domain designs.
• Familiarity with DFT insertion, and multi-mode timing constraints.