Power UPF Methodology Engineer

Summary

Posted: Jan 14, 2025

Role Number:200586647

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and groundbreaking efforts, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including: – Drive Mixed signal IP power ERC and power intent verification. – Drive coverage of power intent across static and dynamic checking methodologies. – Define and develop power ERC framework for new projects. – Bring up power intent checking flows on new projects. – Drive power intent & power ERC sign-off for tape-out. – Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues.

Minimum Qualifications

• BS and a minimum of 3 years of relevant industry experience

Preferred Qualifications

• We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition.
• Experience in ASIC design flows and custom IP design flows.
• Familiar with basic circuit & layout fundamentals.
• Familiar with Caliber based ERC flows.
• Familiar with power intent definition, implementation and verification flows.
• Knowledge of scripting languages like, Tcl, Perl and Python.
• Familiar with of power analysis and optimization methods.
• Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking)
• Strong communication skills are a pre-requisite as you will collaborate with a lot of different groups.

Pay & Benefits

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 and $264,200, and your base pay will depend on your skills, qualifications, experience, and location.
  
  Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
  
  Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.