Custom Timing Engineer

Summary

Posted: Feb 11, 2025

Role Number:200590754

Do you want to utilize your engineering background to make big things happen? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! Join us, and you’ll help crafting tools that allow us to bring customers experiences they’ve never before envisioned! We have an extraordinary opportunity for Circuit Timing Engineers. As part of the custom digital circuits team you will time and design sophisticated circuits that deliver extraordinary circuit performance while consuming low power which is pivotal to delivering the outstanding products Apple is known for. This is a highly visible role is at the heart of our custom designs.

Description

Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, as well as work with a team of hardworking engineers. As a Circuit Timing Engineer for the custom digital team, you will develop timing models and methodology and will perform the following: – Enable global directives to ensure proper timing of innovative circuit topologies. – Provide a link between circuit designers, tool developers and chip level timing to validate transistor level timing accuracy and timing test correctness. – Develop timing methodology that is crucial to support billions of Apple devices providing high performance in a very small power envelope

Minimum Qualifications

• BS and a minimum of 10 years of relevant industry experience

Preferred Qualifications

• We are looking for applicants with 10+ years of proven experience in transistor level static timing analysis and noise flows as well as the following:
• Expertise and in depth knowledge of industry standard STA tools, Nanotime and Primetime.
• Experience in timing constraints generation & management, and timing convergence in the CPU environment.
• Familiarity with custom memory designs (SRAM/ register file / dynamic circuits).
• Ability to perform spice simulations for correlation to static timing and noise results.
• Expertise in analyzing and converging crosstalk delay and noise glitch in deep submicron processes.
• Good interpersonal skills.
• Scripting skills for flow automation; experience with tcl is a plus.
• Knowledge of industry standard circuit and design tools.
• MSEE preferred