CPU RTL Engineer

Summary

Posted: Oct 24, 2024

Role Number:200575215

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring dedicated engineers for CPU architecture and microarchitecture development targeted for low power mobile devices.

Description

As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification • RTL feature ownership – development, assessment and refinement of new RTL features to target power, performance, area and timing goals • Validation – support test bench development and simulation for functional and performance verification Performance exploration and correlation – explore high performance strategies and validate that the RTL design meets targeted performance • Design delivery – work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power

Minimum Qualifications

• Minimum BS and 3+ years of relevant industry experience
• Knowledge of microprocessor architecture, including experience with at least one of the following: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, or cache and memory subsystems
• Knowledge of Verilog or VHDL
• Experience with simulators and waveform debugging tools
• Knowledge of logic design principles

Preferred Qualifications

• Understanding of timing, power and area tradeoffs in CPU microarchitecture
• Understanding of low power and high performance microarchitecture techniques
• Experience using an interpretive language such as Perl or Python