Circuits Physical Design Engineer

Summary

Posted: Nov 21, 2024

Role Number:200579941

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on silicon validation, making a critical impact delivering products to market quickly.

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure & signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation.

Minimum Qualifications

• BS and a minimum of 3 years of relevant industry experience.

Preferred Qualifications

• We are looking for applicants with at least 3 years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Familiar with development of block/partitions for silicon validation of foundation Ips.
• Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is a strong plus.
• Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is a strong plus.
• Hands-on experience with ECO implementation, both functional and timing closure is a strong plus.
• Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
• Strong scripting skills using Perl/Tcl.
• Strong written/verbal communication skills.