Analog Layout Engineer

Summary

Posted: Feb 11, 2025

Weekly Hours: 40

Role Number:200590743

Apple Silicon Engineering Group (SEG) is seeking Analog Layout Engineers to work on the next generation of Apple’s systems-on-chip (SOCs)! These SOCs, with multi-billion transistors, serve as the core of iPhones and iPads. We focus on Analog/Mixed-Signal (AMS) circuits, including SerDes for data communication, PLLs for clock generation, and sensors for measuring all sorts of physical quantities. Analog Layout Engineers are essential in transforming design ideas into silicon, collaborating with circuit designers, and using sophisticated tools and methodologies. The work we do involves crafting custom analog designs to optimize the performance of our world-class products. This fast-paced work environment has endless learning opportunities and collaboration across dedicated multidisciplinary teams. Are you a self-motivated engineer passionate about working with ground breaking technology? If you want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products, this could be the role for you! The roles include crafting upcoming products, challenging oneself, and broadening skills in a dynamic, innovative work culture.

Description

Layout Engineers are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop world-leading SOCs. As a part of the AMS layout team you will be delivering fully-verified, layout. This includes the following: Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floorplans and intricate circuits. Running complete sets of design verification tools available on AMS blocks. Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.

Minimum Qualifications

• B.S. and a minimum of 10 years relevant industry experience or equivalent

Preferred Qualifications

• 10+ years in analog/mixed-signal layout design of deep submicron CMOS circuits, with at least 3+ years in FinFET technologies.
• Experience implementing analog layout designs to achieve tight matching, low noise, and low power consumption. Design components include CMOS, BJTs, resistors, capacitors, pad IOs, and ESD.
• Must recognize failure-prone circuit and layout structures, have experience with analog and DFM standard methodologies, and proactively work with the circuit design team to identify the best approach to solving problems.
• High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
• Technical understanding of IR drop, RC delay, electro-migration, self-heating, and coupling capacitance.
• Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.)
• Experience using Cadence Virtuoso’s advanced features (XL, EAD, APR, and Constraint Manager)
• Programming/scripting knowledge in SKILL, Perl, TCL, Shell and/or Python
• Excellent communication skills and ability to work with multi-functional teams.
• Additional skill (plus): Cadence Innovus, CAD Automation experience, PCell creation experience, or familiar with Machine Learning and AI concepts
• Concentration in Mixed-Signal and RF Integrated Circuits is helpful