Design Verification Engineer

Summary

Posted: Oct 31, 2024

Role Number:200455215

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there’s no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple’s Hardware Technology organization, and we’d love to have you join us.

Description

As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP: – Neural Engine hardware – DRAM subsystem, memory controller logic – Encode and Decode systems for ProRes and other codec formats such as VP9, AV1 – Hardware security, including cryptographic algorithm implementations – High-Speed IO standards such as PCI Express, DisplayPort, MIPI – Power management and fabric infrastructure – Memory cache management – Display Subsystem for variety of panels and products These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!

Minimum Qualifications

• Minimum of BS + 3 years relevant industry experience.

Preferred Qualifications

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
• Knowledge of SystemVerilog, digital simulation and debug
• Knowledge of computer architecture and digital design fundamentals
• SW programming skills with knowledge of data structures and algorithms
• Experience with Python, Perl, or similar scripting language
• Ability to work independently to deliver the project goals
• Knowledge of verification methodologies like UVM
• Experience with C/C++, assembly is a plus
• Excellent interpersonal skills and the dream to tackle diverse challenges

Pay & Benefits

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 and $264,200, and your base pay will depend on your skills, qualifications, experience, and location.
  
  Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
  
  Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.