Cellular SOC Design Verification Engineer – Entry Level

Summary

Posted: Oct 9, 2024

Role Number:200552149

Do you have a passion for invention and self-challenge? This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Apple’s Silicon Engineering Group has embarked upon to-date. As a Design Verification Engineer on our team, you’ll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state-of-the-art Cellular SoCs! You will have the opportunity to contribute to the verification effort of a set of complex SOCs delivering the Cellular solution. You will integrate multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM based test bench, implement effective coverage driven and directed test suites, deploy new tools and methodologies to deliver chips that are right-first-time. By collaborating with other product development groups across Apple, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world!

Description

Through this experience, you will learn all aspects of a large scale SOC design, Complex verification test benches, different types of SOC architectures, multiple high speed protocols, industry-standard low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Cellular protocol, FW- HW interactions, complexities of multi-chip SOC debug architecture, etc.

Minimum Qualifications

• BS and a minimum of 3 years of relevant industry experience is required.

Key Qualifications

• MS in EE or CS. Coursework in Digital Design, Computer Architecture, Object Oriented Programming, Networking Protocol. Programming experience in SystemVerilog or Python or C++ or Java.
• Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.