CAD Engineer, Logic Equivalence & ECO

Summary

Posted: Oct 3, 2024

Role Number:200571559

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? Imagine the delight in knowing your efforts were critical in the implementation of system-on-chip (SoC) designs in the next generation of Apple products! In this exciting role, you will develop, maintain, and enhance logic equivalence checking flows. You will architect, design, and implement the software and methodologies that design teams use to verify designs and complete ECOs. You will develop, maintain, and enhance machine learning and generative AI solutions to improve logic equivalence flows. You will work directly with EDA vendors to design new tool features, and you will directly own logic equivalence signoff on tape outs.

Description

In this highly visible role, your primary responsibilities will include: – Developing, maintaining, and enhancing CAD applications for logical equivalence. – Supporting frontend design closure , ECO verification, and flow signoff. – Triaging and solving CAD flow problems, and working around EDA tool problems. – Working directly with EDA vendors to resolve tool issues, and identifying enhancements. – Working directly with EDA vendors to architect new tool features and methodologies. – Collaborating with other CAD engineers, including synthesis, DV, analytics, and signoff to build integrated flows. – Participating and engaging with cross functional teams to tackle key logic equivalence challenges. – Using ML and GenAI based solutions to improve CAD applications.

Minimum Qualifications

• Experience with ASIC Design EDA Tools, CAD flows, and/or ASIC design methodologies.
• Knowledge of Tcl, Python or Perl scripting languages.
• Knowledge of Verilog or SystemVerilog coding for hardware design or verification.
• Minimum requirement of BS and 3+ years of relevant industry experience.

Preferred Qualifications

• Strong proficiency in scripting languages, such as Python, Perl, and TCL
• Excellent communication skills, including previous customer support experience
• Excellent interpersonal skills, including collaboration, inclusivity, active listening, and a growth mindset.
• Expertise in industry standard equivalence checking EDA tools
• Expertise in industry standard ASIC synthesis EDA tools
• Understanding of frontend digital design methodologies, including simulation, synthesis, RTL linting, low power verification, BIST, DFT, design integration, and frontend signoff.
• Experience architecting and implementing CAD flows
• Comfort within Linux/Unix environments.
• Understanding of software engineering practices (agile, code reviews, unit level testing, regression testing).
• Familiarity with current Gen AI research in one of the following areas: RAG, Semantic Search, or Prompt Engineering is a plus

Pay & Benefits

• At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 and $264,200, and your base pay will depend on your skills, qualifications, experience, and location.
  
  Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
  
  Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.